1. Field of the Invention
The present invention relates to a data output circuit, and more particularly, to a data output circuit employing a delay locked loop used in a synchronous semiconductor device.
2. Description of the Related Art
In general, synchronous semiconductor devices output data in synchronization with an external clock signal. For the synchronization, delay locked loops (DLLs) including a delay unit and a phase detection unit have been widely used. The delay locked loop delays the external clock signal by a predetermined time period to generate an internal clock signal. More specifically, the phase detection unit detects a phase difference between the external clock signal and a replica data strobe signal output from a data strobe signal replication unit. The delay unit changes the delay time in response to the phase difference detected by the phase detection unit and delays the external clock signal by the changed delay time to generate the internal clock signal. The data strobe signal replication unit delays the internal clock signal by a predetermined time period to output the replica data strobe signal. Here, by using the internal clock signal, the delay time of the data strobe signal replication unit is set to be equal to the delay time of the data strobe signal output unit for outputting the data strobe signal.
FIG. 1 is a block diagram showing a conventional data output circuit. The conventional data output circuit comprises an internal clock generation unit 10 including the DLL circuit, a data strobe signal output unit 20, and a data strobe signal replication unit 30. The internal clock generation unit 10 is constructed using a delay unit 12 and a phase detection unit 14.
Now, functions of the blocks shown in FIG. 1 will be described.
In response to an external clock signal CLK externally input and a replica data strobe signal DQR output from the data strobe signal replication unit 30, the internal clock generation unit 10 delays the external clock signal CLK by a first delay time to output an internal clock signal ICLK.
The phase detection unit 14 compares a phase of the external clock signal CLK with a phase of the replica data strobe signal DQR to output a control signal con. In response to the control signal con, the delay unit 12 changes the first delay time and delays the external clock signal CLK by the changed first delay time to output the internal clock signal ICLK. In other words, the delay time of the delay unit 12 is adjusted by the control signal con.
The data strobe signal output unit 20 outputs the data strobe signal DQS by using the internal clock signal ICLK. At this time, the internal clock signal ICLK is delayed through a predetermined number of gate stages in the data strobe signal output unit 20. Therefore, the output data strobe signal DQS is delayed by a predetermined time with reference to the internal clock signal ICLK. In general, in a semiconductor device, the delay time of the data strobe signal output unit 20 is set so that the data strobe signal DQS can be synchronized with the output data signal.
The data strobe signal replication unit 30 delays the internal clock signal ICLK by the delay time of the data strobe signal output unit 20, that is, a time by which the data strobe signal DQS is delayed with reference to the internal clock signal ICLK in the data strobe signal output unit 20, and outputs the replica data strobe signal DQR.
FIG. 2 is an operational timing diagram for explaining operations of the conventional data output circuit shown in FIG. 1. In FIG. 2, CLK denotes an external clock signal, ICLK denotes an internal clock signal, DQ denotes a data signal, DQS denotes a data strobe signal, and DQR denotes a replica data strobe signal. In addition, in FIG. 2, tDLL denotes a first delay time, that is, a time by which the external clock signal CLK is delayed through the internal clock signal generation unit 10; tCLK denotes a time by which the data strobe signal DQS is delayed with reference to the internal clock signal ICLK in data strobe signal output unit 20; and tREP denotes a second delay time, that is, a time by which the internal clock signal ICLK is delayed through the data strobe signal replication unit 30.
Now, the operations of the conventional data output circuit will be described with reference to FIG. 2.
The delay unit 12 delays the external clock signal CLK by the first delay time tDLL to output the internal clock signal ICLK. As described above, the first delay time tDLL is adjusted by the control signal con output from the phase detection unit 14.
The data strobe signal output unit 20 uses the internal clock signal ICLK to output the data strobe signal DQS. At this time, the output data strobe signal DQS is delayed by a predetermined time tCLK with reference to the internal clock signal ICLK. Here, the data strobe signal output unit 20 is designed so that the phase of the output data strobe signal DQS can be equal to the phases of the data signals DQ.
The data strobe signal replication unit 30 delays the internal clock signal ICLK by the second delay time tREP to output the replica data strobe signal DQR. Here, the data strobe signal replication unit 30 is designed so that the second delay time tREP can be equal to the delay time tCLK of the data strobe signal output unit 20.
The phase detection unit 14 detects a phase difference between the replica data strobe signal DQR and the external clock signal CLK and outputs the control signal con for adjusting the delay time tDLL of the delay unit 12. More specifically, if the phase of the replica data strobe signal DQR leads the external clock signal CLK, the delay time tDLL is increased to allow the phase of the internal clock signal ICLK to lag behind, so that the phase of the replica data strobe signal DQR can lag behind. On the contrary, if the phase of the replica data strobe signal DQR lags behind the external clock signal CLK, the delay time tDLL is decreased to allow the phase of the internal clock signal ICLK to lead, so that the phase of the replica data strobe signal DQR can lead.
In other words, the internal clock generation unit 10 delays the external clock signal CLK so that the phases of the replica data strobe signal DQR and the external clock signal CLK can be equal to each other, and generates the internal clock signal ICLK. If the delay time tCLK of the data strobe signal output unit 20 and the delay time tREP of the data strobe signal replication unit 30 are equal to each other, the phases of the replica data strobe signal DQR and the data strobe signal DQS are also equal to each other, so that the phases of the replica data strobe signal DQR and the data signal DQ are equal to each other. Therefore, if the internal clock signal ICLK is generated as described above, the phase of the data signal DQ can be synchronized with the external clock signal CLK.
In other words, in order to synchronize the data signal DQ and the external clock signal CLK, the delay time tCLK of the data strobe signal output unit 20 and the delay time tREP of the data strobe signal replication unit 30 must be equal to each other. If the two delay times tCLK and tREP are different from each other, the data signal DQ and the external clock signal CLK are not synchronized with each other. As a result, there may occur mis-operation in other semiconductor devices receiving the data signal DQ in accordance with the external clock signal CLK. The process for equalizing the two delay times tCLK and tREP is not a simple one.
FIG. 3 is an operational timing diagram showing cases where the delay time tCLK of the data strobe signal output unit 20 and the delay time tREP of the data strobe signal replication unit 30 are different from each other. FIG. 3A shows a case where the delay time tREP of the data strobe signal replication unit 30 is longer than the delay time tCLK of the data strobe signal output unit 20, and FIG. 3B shows a case where the delay time tREP of the data strobe signal replication unit 30 is shorter than the delay time tCLK of the data strobe signal output unit 20.
Firstly, referring to FIG. 3A, in a case where the delay time tREP of the data strobe signal replication unit 30 is longer than the delay time tCLK of the data strobe signal output unit 20, the phase of the internal clock signal ICLK leads, so that the output time point of the data signal DQ can lead. If a different semiconductor device receiving the output data signal DQ senses the data signal DQ at intermediate time points t1 and t2 of the external clock signal CLK, invalid data may be sensed as shown in FIG. 3A.
Next, referring to FIG. 3B, in a case where the delay time tREP of the data strobe signal replication unit 30 is shorter than the delay time tCLK of the data strobe signal output unit 20, the phase of the internal clock signal ICLK lags behind, so that the output time point of the data signal DQ can lag behind. Similarly, if another semiconductor device receiving the output data signal DQ senses the data signal DQ at intermediate time points t1 and t2 of the external clock signal CLK, invalid data may be sensed as shown in FIG. 3B.
The aforementioned problem also occurs in a case where the other semiconductor device senses the data signal DQ at rising and falling edges of the external clock signal CLK. The problem becomes more serious as the operation speed of the semiconductor device increases. Therefore, it is important to equalize the delay time tREP of the data strobe signal replication unit 30 and the delay time tCLK of the data strobe signal output unit 20.
Conventionally, in order to equalize the delay time tREP of the data strobe signal replication unit 30 and the delay time tCLK of the data strobe signal output unit 20, modeling and simulation of the data strobe signal output unit 20 are performed to estimate the delay time tCLK of the data strobe signal output unit 20, and the delay time tREP of the data strobe signal replication unit 30 is determined with reference to the estimated value. In addition, in order to correct a modeling error and a process-changing error, options such as a fuse for adjusting the delay time tREP are provided to the data strobe signal replication unit 30, and the adjustments are made at a package level.
However, it is generally difficult to obtain an accurate modeling of the data strobe signal output unit 20. In addition, a large amount of time is required for performing the simulation using the modeling. In other words, the aforementioned conventional method has shortcomings in that it is difficult to accurately determine the delay time tREP of the data strobe signal replication unit 30 and too much time is required for an accurate determination of the delay time.
In addition, although the modeling error and the process-oriented error can be corrected at the package level, it is impossible to adjust a difference between a plurality of packages fabricated from a single, common wafer.
Therefore, in the conventional data output circuit, there is a high probability of errors occurring between the delay time tREP of the data strobe signal replication unit 30 and the delay time tCLK of the data strobe signal output unit 20. As a result, a semiconductor device receiving the output data may receive invalid data. These problems become more serious as the operation speed of the semiconductor device increases.